1. Field of the Invention
The present invention is directed to the field of semiconductor processing, and, more particularly, to a method of controlling an etching process used on multiple dielectric layers on a semiconductor device.
2. Description of the Related Art
There is a constant drive to reduce the size, or scale, of transistors to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. A conventional integrated circuit device, such as a microprocessor, is typically comprised of many millions of transistors formed above the surface of a semiconducting substrate. For the integrated circuit device to function, the transistors must be electrically connected to one another through conductive interconnections.
Many modern integrated circuit devices are very densely packed, i.e., there is very little space between the transistors formed above the substrate. Thus, these conductive interconnections are typically made in multiple layers to conserve plot space on the semiconducting substrate. This is typically accomplished through the formation of a plurality of conductive lines and conductive plugs formed in alternating layers on the device. As is readily apparent to those skilled in the art, the conductive plugs are means by which various layers of conductive lines, and/or semiconductor devices, may be electrically coupled to one another. The conductive lines and plugs may be made of a variety of conductive materials, such as copper, aluminum, aluminum alloys, titanium, tantalum, titanium nitride, tantalum nitride, tungsten, etc.
One problem associated with modern integrated circuit devices is that, due to the reduced size of transistors and the very dense packing of transistors on an integrated circuit device, there is an increase in the capacitance between conductive lines formed on the integrated circuit device. The increased capacitance is undesirable because it slows down the operating speed of the integrated circuit device. This line-to-line capacitance is directly proportional to the distance between adjacent lines as well as the dielectric constant of the material positioned between the adjacent conductive lines. In the densely packed integrated circuits of today, the distance between the various conductive lines is inherently small and increasing that distance is impractical . Thus, in an effort to reduce the line-to-line capacitance, efforts have been made to position material between the adjacent lines that has a relatively low dielectric constant, e.g., a material having a dielectric constant less than approximately four. These materials are sometimes referred to as low-k dielectric materials and include materials such as silane based dielectrics, etc.
However, some of the low-k dielectric materials tend to be non-conformal when deposited. Therefore, a second layer of a dielectric material that is more conformal and tends to produce a flatter surface, e.g., TEOS, is formed above the low-k dielectric layer. Thereafter, openings for conductive interconnections, e.g., lines or contacts, are formed through both the low-k dielectric layer and the second dielectric layer. For example, a via may be formed above a conductive line for a conductive contact that will be electrically coupled to the conductive line below.
The etch rate of the low-k dielectric layers and the second dielectric layers are typically different. For example, a low-k dielectric material may etch at a faster rate than other types of dielectric materials, e.g., TEOS. As a result, problems may arise when the low-k dielectric layer and the second dielectric layer are made to thickness other than the design thickness of such layers, i.e., when the thickness ratio of the layers is other than the ratio anticipated by the design process. A variation in the thickness of each of those layers as compared to the design thickness of each of those layers can have an adverse impact on transistor manufacturing. For example, in the case where the low-k dielectric is thicker than anticipated, performing an etching process based on the assumed design thickness of these layers may be too aggressive. In the described situation, due to variations in the thickness of the layers, the overall etch rate for both layers is faster than the rate anticipated by the design process. This may lead to several problems, such as damage to the underlying structure, oversizing a particular feature defined by the etching process, etc.
Conversely, another situation to consider is when the second dielectric layer, the layer with the slower etch rate, is thicker than anticipated by the design process and the low-k dielectric layer is thinner than the design thickness of that layer. In that situation, performing a standard etching process that is based upon the assumed design thickness of those layers, may result in insufficient etching, i.e., the feature may not be completely defined because of the increased thickness of the second dielectric layer. In effect, the overall etch rate is slower than anticipated by the design process. This situation may lead to costly and time consuming re-work to properly define the desired features, i.e., additional etching may need to be performed.
The present invention is directed to a method of manufacturing a semiconductor device that minimizes or reduces some or all of the aforementioned problems.